The present invention generally relates to an arithmetic logic unit for performing many different kinds of digital arithmetic operations. The present invention more particularly relates to such an arithmetic logic unit for use in a digital signal processor and which performs operations such as operand shifts, operand masks, force zero, operand addition, operand substraction, and overflow detection and correction in an efficient manner.
Arithmetic logic units find application in many different kinds of digital systems such as, for example, calculators and digital signal processors. Arithmetic logic units are called upon to perform many different kinds of digital arithmetic operations. Arithmetic logic unit operations are generally performed on multiple-bit operands and may include operand shifts, operand masks, force zero, operand addition, operand subtraction, and overflow detection and correction.
Arithmetic logic units generally perform these operations under the control of operating instructions received from an instruction memory such as an instruction read only memory (IROM). Each instruction provided by the instruction memory corresponds to one operating cycle of the arithmetic logic unit. The number of operating cycles required by an arithmetic logic unit to perform its operations is very important and should be kept to the lowest number of operating cycles possible for high efficiency processing.
High efficiency arithmetic logic unit performance is most desirable where operating speed is of importance, such as in a digital signal processor application. High efficiency arithmetic logic unit performance is also equally as important where the arithmetic logic unit is utilized in portable equipment which is powered by a depletable power source such as a battery. As the number of operating cycles required by an arithmetic logic unit to perform its operations is reduced, the power consumption of the depletable power source attributable to the arithmetic logic unit is correspondingly reduced. This, as a result, extends the time of operation of the portable equipment before battery replacement or battery recharging is necessary.
The present invention provides an improved arithmetic logic unit for performing a number of different digital arithmetic operations in an efficient manner thus requiring a reduced number of operating cycles. As will be seen hereinafter, the arithmetic logic unit of the present invention can perform operand sign forcing, operand shift with or without sign forcing, operand mask, operand shift with sign forcing and two's compliment inversion, and operand addition and substraction with or without overflow detection and correction in only one operating cycle. An example of the above will be described in connection with a rather complex addition of two operands in only four operating cycles where sign forcing, operand shifting, two's compliment inversion, operand addition, and masking operations are required.